Photolithography is the one of the most important process used in IC manufacturing to record a binary image on a layer of photosensitive material spun over a substrate, generally a semiconductor wafer.
Some of the most advanced semiconductor fabs depend on state of art data monitoring and analysis techniques to be certain that the wafers result in high yields for memory and logic devices. These methods evolve from a periodic sampling of partially processed wafers within the production sequence and blank silicon or test wafers to check for particles or defects generated from a specific process tool.
To identify the production issues and to facilitate yield improvement, a fab has to make many timely decision such as sampling interval (exact step in the production cycle where a wafer is sampled) and sampling rate (frequency of measurement step a wafer is measured) to ascertain the most cost-efficient system.
To be able to better cater to fabs needs, OEMs are fitting the process equipment with monitors and sensors that effectively reduce the interval, rate of sampling and measuring wafers. These in-line monitors are productively emulating the on-wafer measurements.With better interpretation of tool sensor information and its effects on the wafers, the system provides better quality output.
The state of art fabs depend on this process tool information to create a fab-wide Fault Detection and Classification (FDC) system which collects real time equipment data, analyzes and compares them against “Golden” data.
Einnosys offers a great Fault Detection and Classification (FDC) software system that is flexible and can be configured to your needs. You can find more information at https://einnosys.com/fault-detection-classification-fdc/.
During this whole process if the system detects poor quality the system automatically stops wafer processing.As the fab becomes more competent and knowledge rich, this in turn leads to higher efficiency by lowering cost and increased yield. The absence of this level and granularity of data process troubleshooting in the litho cell requires significant time to identify sources of deviation for corrective action. Corrective action requires physical inspection of the various components.
In addition, feedback from metrology equipment for overlays and critical dimensions can further help improve yield and cycle time. Auto analysis of overlay data and feeding them back into the steppers and result in significant time saving for lithography engineers.
Einnosys has had many decades of experience working with many different make and models of lithography equipment such as steppers from Canon, ASML and Nikon, tracks from TEL, SVG and DNS and metrology equipment from KLA-Tencor, Rudolph and Inspectrology.
In addition, creating stepper jobs automatically from the circuit data stored in CAD system can eliminate human errors in creating stepper jobs and further improve yield. Einnosys staff has created stepper jobs automatically by pulling data from the CAD system and then transferred them to steppers through EIRMS – Recipe Management System that is similar to JobServer. For more information, visit https://einnosys.com/recipe-management-system-2/.